1. Field of the Invention
Embodiments of the present invention generally relate to the fabrication of integrated circuits. More specifically, embodiments of the invention pertain to methods of removing residue from the interior surfaces of a substrate processing chamber.
2. Description of the Related Art
The manufacture of modern logic, memory, or linear integrated circuits (ICs) typically requires more than four hundred process steps. A number of these steps are thermal processes that raise the temperature of a semiconductor wafer to a target value to induce rearrangements in the atomic order or chemistry of thin surface films (e.g., diffusion, oxidation, recrystallization, salicidation, densification, flow).
Ion implantation is a preferred method for introduction of chemical impurities into semiconductor substrates to form the pn junctions necessary for field effect or bipolar transistor fabrication. Such impurities include p-type dopants such as boron (B), aluminum (Al), gallium (Ga), beryllium (Be), magnesium (Mg), and zinc (Zn) and N-type dopants such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), selenium (Se), and tellurium (Te). Ion implantation of chemical impurities disrupts the crystallinity of the semiconductor substrate over the range of the implant. At low energies, relatively little damage occurs to the substrate. However, the implanted dopants will not come to rest on electrically active sites in the substrate. Therefore, an “anneal” is required to restore the crystallinity of the substrate and drive the implanted dopants onto electrically active crystal sites. As used herein, “annealing” refers to the thermal process of raising the temperature of an electrically inactive implanted region from an ambient temperature to a maximum temperature for a specified time and cooling to ambient temperatures for the purpose of creating electrically active regions in a device. The result of such annealing and/or the annealing process is sometimes also referred to as “implant annealing,” “activation annealing,” or “activation.” Conventional thermal processes such as rapid thermal processing (RTP) and spike annealing are the main dopant activation methods.
During the processing of the wafer in, for example, an RTP chamber, the wafer may tend to outgas impurities implanted in the wafers. These outgassed impurities may be the dopant material, a material derived from the dopant material, or any other material that may escape the substrate during the annealing process, such as the sublimation of silicon. The outgassed impurities may deposit on the colder walls and on the reflector plate of the chamber. This deposition may interfere with temperature pyrometer readings and with the radiation distribution fields on the wafer, which in turn affects the temperature at which the wafer is annealed. Deposition of the outgassed impurities may also cause unwanted particles on the wafers and may also generate slip lines on the wafer. Depending on the chemical composition of the deposits, the chamber must be taken offline for a “wet clean” process after between about 200 and about 300 processed wafers. The wet clean process requires manual intervention to clean the deposited material from the chamber walls and from the reflector plate, which may be labor intensive and requiring the chamber to be offline for about four hours. There therefore exists a need for an automated method for removing deposits on the chamber walls and reflector plate to increase mean wafers between clean (MWBC).